1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device comprising a plurality of memory cells disposed in the form of a matrix, a plurality of bit line pairs each provided for each column of the memory cells and connected in common to the memory cells of that column and a plurality of column switch circuits each provided for each pair of bit lines to be used for selecting a single bit line pair from among the plurality of bit line pairs.
2. Description of the Related Art
In a semiconductor memory device, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM), memory cells are disposed in the form of a matrix. In order to enter and emit data to and from a specific memory cell, it is necessary to specify that memory cell by using a coordinate value defined by the row and column. To this end, each memory cell is connected to one of a plurality of word lines, which extend in the direction of the line, and one of a plurality of pairs of bit lines, which extend in the direction of the column. Since the pair of bit lines is used not only for specifying the memory cell, but also for transferring data to be entered and emitted, a sense amplifier and precharger circuit is connected to it. Since a single sense amplifier is generally provided corresponding to the plurality of bit line pairs, it is necessary to select a pair of bit lines connected to the sense amplifier from among these plural pairs of bit lines and, to this end, a column switch is provided for each pair of bit lines.
FIG. 1 is a block wiring diagram of a semiconductor memory device using three NMOS transistors for each column switch circuit. In this semiconductor memory device, addresses A.sub.0 to A.sub.n are entered, and it is arranged so that, in order to access a specific one of the memory cells disposed in the form of the matrix, a specific row is selected by less significant address bits, and a specific column is selected by more significant address bits. Although, in this figure, for the convenience of description, four memory cells 51.sub.1 through 51.sub.4 are shown disposed along 2.times.2 rows/columns, the following description subsists also for semiconductor memory devices of large capacity such as 1 Mbits.
In this semiconductor memory device, there is provided row address decoder circuit 57 to which the less significant address bits are entered, column address decoder circuit 58 to which the more significant address bits are entered and address transition detecting circuit 56 for detecting the transition of the address value. From line address decoder circuit 57, two word lines W.sub.0 and W.sub.1 corresponding to the number of rows are outputted and, from column address decoder circuit 58, two column switch selecting signals S.sub.0 and S.sub.1 corresponding to the number of columns are outputted. Four memory cells 51.sub.1 to 51.sub.4 disposed in 2.times.2 are each connected to one of two word lines W.sub.0 and W.sub.1 and to one of the two pairs of bit lines BL.sub.0 /BL.sub.0 and BL.sub.1 /BL.sub.1. Precharger circuits 52.sub.1 and 52.sub.2 are each connected to one end portion of bit line pairs BL.sub.0 /BL.sub.0 and BL.sub.1 /BL.sub.1. Column switch circuits 53.sub.1 and 53.sub.2 are each connected to the other end of each bit line pair BL.sub.0 /BL.sub.0 and BL.sub.1 /BL.sub.1. These column switches 53.sub.1 and 53.sub.2 are intended to connect one of two bit line pairs BL.sub.0 /BL.sub.0 and BL.sub.1 /BL.sub.1 to the data line pair DL/DL. These switch circuits 53.sub.1 and 53.sub.2 are controlled by column switch selecting signals S.sub.0 and S.sub.1, respectively. One end of data line pair DL/DL is connected to both column switch circuits 53.sub.1 and 53.sub.2 in common, and the other end is connected to sense amplifier circuit 55 via precharger circuit 54. Sense amplifier 55 outputs a binary signal to data bus DB depending on which of two data lines DL and DL, which constitute data line pair DL/DL, is higher in potential. Data latch/output buffer circuit 59 having data output terminal D.sub.out for emitting data to the outside is provided at the output side of sense amplifier circuit 55.
Here, while the bit line pair, word line and column switch selecting signal are generally denoted, their subscript is omitted and represented by BL/BL and W and S, respectively. Bit line pair BL/BL comprises bit lines BL and BL. As can readily be understood by those skilled in the art, when the data is entered or emitted, the potential difference between two bit lines BL and BL, which constitute a bit line pair BL/BL, is changed according to the content of that data.
Column switch circuits 53.sub.1 and 53.sub.2 are each comprised of three NMOS field effect transistors M.sub.1 through M.sub.3. One bit line BL of bit line pair BL/BL is connected to the gate of first transistor M.sub.1, and the drain of this transistor M.sub.1 is connected to one data line DL of the data line pair DL/DL. On the other hand, the other bit line BL is connected to the gate of second transistor M.sub.2, and the drain of this transistor M.sub.2 is connected to the other data line DL. The sources of these two transistors M.sub.1 and M.sub.2 are connected in common and grounded via a channel of third transistor M.sub.3. Entered to the gate of this third transistor M.sub.3 is column switch selecting signal S from column address decoder circuit 58. As will be apparent to those skilled in the art, when third transistor M.sub.3 is turned ON, first and second transistors M.sub.1 and M.sub.2 each function as a common source amplifier to form a differential amplifier by these two transistors M.sub.1 and M.sub.2.
As shown in FIG. 2, precharger circuits 52.sub.1, 52.sub.2 and 54 are each comprised of three MOS field effect transistors (MOS FET) M.sub.91 to M.sub.93, to the gate of which precharger circuit activating pulse signal P is supplied from address transition detecting circuit 56. When this pulse signal P is low, each of bit line pairs BL.sub.0 /BL.sub.0. BL.sub.1 /BL.sub.1 or data line pair DL/DL is precharged to a predetermined voltage value.
Next, the operation of this semiconductor memory device is described. If address signals A.sub.0 to A.sub.n are changed, their change is detected by address transition detecting circuit 56, which, as shown in FIG. 3, outputs word line activating pulse signal XE, sense amplifier activating pulse signal SE and precharge circuit activating pulse signal P according to a predetermined timing. In other words, after the address value is changed, first, word line activating pulse signal XE is outputted (time t.sub.1 ) and, a little later (time t.sub.2), sense amplifier circuit activating pulse signal SE and precharge circuit activating pulse signal P are outputted. After word line activating pulse signal XE drops, at time t.sub.3, the rest of pulse signals SE and P also drop, and all of pulse signals XE, SE and P are returned to their original state.
Column address decoder circuit 58 directly reflects the state of the more significant address bit on column switch selecting signal S. If the more significant bit takes a value indicating a specific column, then selecting signal S corresponding to that column is always high, and selecting signal S corresponding to the other column is low.
If the address is changed and word line activating pulse signal XE is emitted, then row address decoder circuit 57 decodes the less significant bit of address signals A.sub.0 through A.sub.n. Word line W corresponding to the decoded value retains the low state when pulse signal XE is low, and shifts to the high state when pulse signal XE is high. It is obvious that word line W not corresponding to the decoded value remains low. Actually, because of the presence of some time delay, the change of pulse signal XE precedes that of word line W. Here, if the difference between times t.sub.1 and t.sub.2 is preset to equal this delay time, then, if word line W is high, precharger circuit activating pulse signal P is turned high while, if word line W is low, then pulse signal P is also turned low. Since bit lines BL, BL and data lines DL, DL are precharged when pulse signal P is low, they are precharged before word line W is turned high, and no electric charge is supplied to them when word line W is high.
If, in this manner, word line W is turned high and is not precharged, a memory cell corresponding to high word line W is selected, and the data of the selected memory is emitted to bit line pair BL/BL. In this case, the potential of one of bit lines BL, BL is reduced depending on the data stored within the memory cell. Then, when word line W is changed from the high to the low state, precharging is initiated again, and the bit line whose potential has been lowered is also returned to its original potential.
On the other hand, if column switch selecting signal S becomes high by the operation of column address decoder circuit 58, then third transistor M.sub.3 is turned ON at the column switch circuit corresponding to selecting signal S. In this state, since first and second transistors M.sub.1 and M.sub.2 cooperatively function as a single differential amplifier, the difference between the drain potentials of first and second transistors M.sub.1 and M.sub.2 will end up in an amplification of the difference between the gate potentials, that is, the potential difference between bit lines BL, BL. In consequence, the amplified signal of selected bit line pair BL/BL is transmitted to data line pair DL/DL. Since selected signal S is established before word line W is turned high, the above-described amplified potential change of bit line pair BL/BL, which was selected by selection signal S, is transmitted to data line pair DL/DL. This change of data line pair DL/DL is amplified by sense amplifier circuit 55, and is emitted to the outside via latch/output buffer circuit 59 and output terminal D.sub.out. The output of sense amplifier circuit 55 is indicated by DB.
If selection signal S is low, then, irrespective of the signal state of bit line pair BL/BL, third transistor M.sub.3 is cut off without exerting any effect on data line pair DL/DL. Therefore, the data output to the outside does not depend on the state of the non-selected bit line pair BL/BL.
Incidentally, one of the plurality of selection signals S, which is emitted from column address decoder circuit 58, never fails to turn high, and one of the column switch circuits is selected. This selected column switch circuit, any of three transistors M.sub.1 to M.sub.3, is turned ON. Therefore, when the word line is low, that is, precharged, current from precharger circuit 54 of data line pair DL/DL via data lines DL, DL to transistors M.sub.1 to M.sub.3 exists. This current is absorbed into a grounding point connected to transistor M.sub.3.
In this semiconductor memory device, since the column switch is comprised of three NMOS transistors M.sub.1 to M.sub.3 only, the area occupied by the column switch circuit is small, and no layout problem of the device can take place. In other words, it is also possible to dispose the column switch circuit with the same width as that of the memory cell. However, if, as described above, precharging is carried out, since the current always begins to flow from precharge circuit 54 at the side of data line pair DL/DL, current consumption can be increased. As the cycle time is increased, the precharging time occupies a greater ratio. Therefore, the longer the cycle time is, the current flowing from its precharger circuit cannot be neglected. If the bit arrangement which serves as the unit for inputting and outputting the data (the so-called data width) is large, since a plurality of column switch circuits corresponding to that bit arrangement is simultaneously selected, power consumption is further increased.
Therefore, in order to reduce power consumption, it is also conceivable to use a transfer gate for the column switch circuit. FIG. 4 is a block wiring diagram illustrating the arrangement of a semiconductor device which constitutes the column switch circuit with the transfer gate.
This semiconductor memory device, as in the one shown in FIG. 1, comprises four memory cells 71.sub.1 through 71.sub.4 arranged in 2.times.2, precharger circuits 72.sub.1, 72.sub.2, 74, sense amplifier circuit 75, address transition detecting circuit 76, row address decoder circuit 77, column address decoder circuit 78 and data latch/output buffer circuit 79. It is only different from the one shown in FIG. 1 in the arrangement of column switches 73.sub.1 and 73.sub.2 each connected to two pairs of bit lines BL.sub.0 /BL.sub.0 and BL.sub.1 /BL.sub.1.
Each of column switches 73.sub.1 and 73.sub.2 is a known transfer gate comprising two NMOS field effect transistors M.sub.5, M.sub.8, two PMOS field effect transistors M.sub.6, M.sub.7 and inverter M.sub.9. Column switch selecting signal S is entered to the gate of NMOS transistors M.sub.5 and M.sub.8, and selecting signal S inverted by inverter M.sub.9 is entered to the gate of PMOS transistors M.sub.6 and M.sub.7. The channels of transistors M.sub.5 and M.sub.6 are each connected in parallel. To one end of this parallel connection, bit line BL is connected and, to its other end, data line DL is connected. Likewise, the channels of transistors M.sub.7 and M.sub.8 are connected in parallel. At one end of this parallel connection, bit line BL is connected and, at its other end, data line DL is connected. As is apparent from the foregoing description, if column switch selecting signal S is high, then bit line pair BL/BL and data line pair DL/DL are electrically connected and, if selection signal S is low, then BL/BL and DL/DL are electrically cut off.
Next, the operation of this semiconductor memory device is described with reference to the timing chart of FIG. 5. Also in this case, if word line W is turned high, the data of the corresponding memory cell is emitted to bit line pair BL/BL. As in the foregoing description, the time when word line W is changed between the high and low states and the time when precharger circuit activating pulse signal P is changed between the high and low states coincide. If column switch selecting signal S is turned high by column address decoder circuit 78, then each of transistors M.sub.5 to M.sub.8 is turned ON in the column switch circuit corresponding to selecting signal S, and the state of bit line pair BL/BL, which corresponds to that column switch circuit, is transmitted to data line pair DL/DL as is. Since selecting signal S is established before word line W is turned high, the above-described potential change of bit line pair BL/BL, which was selected by selecting signal S, will be transmitted, in the end, to data line pair DL/DL as it is. This change of data line pair DL/DL is amplified by sense amplifier circuit 75, and is emitted to the outside via data latch/output buffer circuit 79 and output terminal D.sub.out.
In this semiconductor memory device, one of the plural selecting signals S from column address decoder circuit 78 never fails to turn high, and the column switch circuit corresponding to high selecting signal S is turned ON. However, since the turned-on column switch circuit is precharged from not only bit line pair BL/BL, but from also data line pair DL/DL except for the time when data is entered or emitted, practically no current passes through this column switch circuit. Therefore, power consumption can be made relatively small. However, since the transfer gate comprising NMOS field effect transistors M.sub.5 and M.sub.8 and PMOS field effect transistors M.sub.6 and M.sub.7 is used for the column switch circuit, it is necessary to allow for a sufficiently large separation width between transistors M.sub.5 to M.sub.8 in order to prevent the latch-up effect. Further, since the diffusion factor of boron, which is used as a P-type impurity, is greater than that of arsenic, which is used as an N-type impurity, the designed size of the PMOS transistor, the length of the channel or the separation interval between the diffusion layers tends to become greater than that of the NMOS transistor. In consequence, this semiconductor memory does not allow the column switch circuit to be made small in size, which causes a layout problem. In other words, it is extremely difficult to dispose the column switch with the same width as the disposing interval between the memory cells.